The Electronics and IT Ministry(Meity) aims to train over 85,000 engineers on chip design by expanding the infrastructure available for the technology to 120 academic institutions across the country in the next five years, an official statement said on Wednesday.
The electronics and IT ministry had done a pilot deployment in 2021 under special manpower development programme for Chips to System Design (SMDP-C2SD), wherein a centralized design facility at state-run C-DAC was enabled for remote access by over 50,000 engineering students at 60 academic institutions for designing chips.
“Leapfrogging, Meity now intends to make accessible a centralized chip design infrastructure to be made available at India Chip Centre setup at C-DAC, to train over 85000 B Tech, M Tech and PhD students at 120 academic institutions across the country in chip design area for next 5 years,” an official statement said.
For making available the chip design infrastructure at India Chip Centre of C-DAC, leading industry vendors from EDA (Electronic Design Automation), Electronic Computer-Aided Design (ECAD), IP Core and Design solutions Industry are being partnered with.
“Specific collaborative arrangements are being made available with Synopsys, Cadence Design Systems, Siemens EDA, Silvaco and other leading tool vendors, IP & design solution providers and Fab aggregators,” the statement said.
As SemiconIndia 2022 concluded successfully last week, most of the global semiconductor leaders like Intel, Micron, Qualcomm, LAM Research etc not only highlighted the contribution of their Indian research and development centres, which are now the biggest centres out of their headquarter locations but also acknowledged the semiconductor design strength in our country, which now makes up for 20 per cent of the world’s engineers.
Electronics and IT minister Ashwini Vaishnaw at Semicon India conferernce had highlighted that India’s democracy and talent pool sets it apart from other countries fighting for chip sovereignty.